Efficient Computer lives up to its name by creating what it describes as the most energy-efficient programmable processor.
The startup emerged by stealth in March 2024 with $16 million in seed funding led by Eclipse VC and claims to have built an entirely new technology stack, from compiler to silicon, in a year.
The company's focus is to create what it describes as a “general-purpose post-Von Neumann processor design that is easy to program and also extremely power efficient.”
Efficient memory structuring.
Brandon Lucia, founder and CEO of Efficient Computer, said: “Today's computers are horribly inefficient. The dominant “von Neumann” processor design wastes 99% of energy. Unfortunately, this inefficiency is deeply rooted in its design. In von Neumann processors, programs are expressed as a sequence of simple instructions, but executing programs in a simple sequence is unacceptably slow. Improving performance requires complex hardware to find instructions that can be safely executed in parallel. Improving efficiency requires a fundamental rethinking of how we design computers.”
What that means in practice is that instead of executing a series of instructions like von Neumann's designs, his architecture “expresses programs as a 'circuit' of instructions that shows which instructions communicate with each other.” This design, called Fabric processor architecture, has been implemented in the Monza test SoC.
Lucía was recently interviewed by eeNews Europe and explained in more detail what the company's approach entails. “What's fundamentally different is that the architecture was developed with a compiler and a software stack at the same time from research at Carnegie Mellon and we designed it with generality in mind,” he said. “We don't need a registration stream and we don't need to get instructions every cycle. A subset of the tiles are also memory access tiles; that is an efficient way to structure memory.”
Initial performance is 1.3 to 1.5 TOPS/W, 500 mW to 600 mW for the chip, but that's just the beginning. “Looking ahead, we have a roadmap to expand architecture as we design space exploration. By early 2025 we will be able to reach 100GOPS at 200MHz and we believe we can scale that performance 10 to 100 times with the same efficiency,” he said in the interview.
