- CXL 3.2 provides a number of key improvements
- Security updates are a major focus for 3.2
- CXL has become increasingly vital in the age of AI
CXL Consortium has announced the release of its new Compute Express Link (CXL) 3.2 specifications, which bring a series of optimized functionalities to the technology.
In its announcement, the consortium revealed that the updated specification will improve the monitoring and management capabilities of CXL memory devices and improve the functionality of CXL memory devices for both operating systems and applications.
Security improvements are also a key talking point with the introduction of the Trusted Security Protocol (TSP).
What to expect from CXL 3.2
CXL plays a crucial role in how GPUs and CPUs interact with memory, helping to standardize communication between devices and reduce delays. In total, this helps make systems faster and more efficient when handling large volumes of data.
With the advent of generative AI, CXL has become increasingly important given the rapid data processing requirements of applications, and this latest update will further improve upon previous specifications, particularly in terms of memory device monitoring and management. CXL.
The new specification will include a new CXL active page monitoring unit (CHMU) aimed specifically at optimizing memory tiering.
Similarly, the consortium revealed support for PCIe Management Message Passing (MMPT) along with improvements to the CXL online firmware.
Security improvements are a key focus in this latest update through TSP, the consortium noted, including new metabit storage features, expanded IDE protection, and improved compliance testing for interoperability.
The consortium also ensured full compatibility with previous CXL specifications.
“We are excited to announce the release of the CXL 3.2 specification to advance the CXL ecosystem by providing improvements to the security, compliance and functionality of CXL memory devices,” said Larrie Carr, president of the CXL Consortium.
“The Consortium continues to develop open and coherent interconnection and enable an interoperable ecosystem for heterogeneous computing and memory solutions.”
